1. Field of the Invention
This invention relates to the design of electronic circuits and more particularly to a CMOS tri-state buffer which connects circuit components having different supply voltages.
2. Description of the Background Art
Recent improvements in semiconductor Complimentary Metal Oxide Semiconductor (CMOS) technology have resulted in extremely narrow channel transistor devices, having lengths of 0.5 .mu.m and less. One advantage of these narrow devices is their ability to be densely packed on integrated circuits (IC's). As circuit designers have exploited this density feature, IC power consumption has increasingly become an important design issue, especially where the goal is to provide low power devices for portable digital equipment. One technique for lowering system power consumption has been to reduce IC power supply voltages from a typical 5 Volts (v), to voltages in the range of 3.0-3.3 V. CMOS IC's designed for use in these low voltage systems require thin gate-oxide transistors in order to maintain high overall device performance. This thin gate oxide limits voltage differences between gate and drain, between gate and source, and between gate and back gate, to limits lower than the voltage maximums of previous transistors which used thicker gate oxide.
The problem created by these thin gate oxide devices is that they are difficult to use in combination with the higher voltage devices in the same digital system, since the power supplies and device output swings employed in the older devices can easily damage the fragile oxide layers of the new high performance devices. A common approach to mixing thin and thick oxide technologies has been to mix the different devices on a single integrated circuit or chip using a special manufacturing process. This customized manufacturing process is expensive and is available for only a limited variety of device types. Since an objective of all commercial designs is to minimize manufacturing costs by using available components and processes where feasible, what is needed is a design for buffering these lower voltage devices in a system which may also use the more common 5V devices.